Sensing device for a passive matrix memory and a read method for use therewith

ABSTRACT

A sensing device ( 10 ) for reading data stored in a passive matrix memory comprising memory cells in the form of ferroelectric capacitors, comprises an integrator circuit ( 11 ) for sensing the current response and means ( 16,17,18 ) for storing and comparing two consecutive read values, one of which is a reference value.  
     In a read method for use with the sensing device a bit line is connected to the sensing device for sensing a charge flowing therebetween and a memory cell at the crossing of the former and an activated word line, whereafter two consecutive reads of the memory cell are performed an integrated over predetermined time periods in order to generate first and second read values which are compared for determining a logical value dependent on the sensed charge.

[0001] The invention concerns a sensing device for reading data storedin a passive matrix memory comprising memory cells in the form offerroelectric capacitors, wherein said sensing device senses a currentresponse corresponding to the data, typically a binary one or a binaryzero, and performs an integration of two read values.

[0002] The invention also concerns a read method for use with thesensing device according to the invention, wherein the sensing deviceare used for reading data stored in a passive matrix memory with wordand bit lines and comprising memory cells in the form of ferroelectriccapacitors at crossings between the word and bit lines, wherein thesensing device senses a current response corresponding to the datastored in a memory cell, typically at binary one or a binary zero, andperforms an integration of read values, wherein the read methodcomprises controlling the electric potentials on all word and bit linesin time latching word line potentials to potentials selected amongpredetermined word line potentials and either latching bit lines topotentials selected among predetermined bit line potentials, wherein bitlines in a read cycle are connected to the sensing device for sensing acharge flowing between a selected bit line and a memory cell at thecrossing of the former and a word line activated by being latched to aselected potential for initializing the read cycle.

[0003] Ferroelectric matrix memories can be divided into two types, onetype containing active elements linked to the memory cells, and one typewithout active elements. In the following focus is directed only towardspassive matrix memories without active elements, such as diodes ortransistors that are locally associated to the memory cells.

[0004] A ferroelectric matrix memory can have memory cells in the formof ferroelectric capacitors without active access elements such as anaccess transistor and comprises a thin ferroelectric material with a setof parallel conducting electrodes (“word lines”) deposited on one sideand an essentially orthogonal set of conducting electrodes (“bit lines”)deposited on the other side. This configuration is referred to as a“passive matrix memory”. In the passive matrix memory, the individualmemory cells are formed at the crossing-points of the opposingelectrodes creating a memory matrix comprising memory cells that can beindividually accessed electrically by selective excitation of theappropriate electrodes from the edge of the matrix.

[0005] To write to a memory cell, a positive or negative voltage isapplied to the electrodes, causing the ferroelectric material to movealong its hysteresis curve to a stable state corresponding to thewritten datum, a binary one or a binary zero. To determine the data thusstored in a ferroelectric capacitor, a voltage (typically in the form ofa voltage pulse) is applied across the plates of the capacitor, wherebya current response is sensed by means of a sensing device, typically asense amplifier. The sensing device is typically connected to arespective bit line, directly or via a multiplexer or gate.

[0006] One of the difficulties during sensing is to establish areference being able to discriminate between a binary zero and a binaryone. One solution is to introduce a reference voltage to the senseamplifier, which is described for instance in U.S. Pat. No. 5 905 671.Any observed signal above the reference is taken as one of two logicstates, while any signal below the reference is taken as the other logicstate.

[0007] However, there are several limits and drawbacks with thedescribed reference method and similar direct reference methods, whichwill be further described below.

[0008] Assuming stable and predictable conditions, a parasiticcontribution may in principle be removed by subtracting a fixed amountof charge from that recorded by the sense amplifier during the readingcycle. In many instances, however, the magnitude and variability of theparasitic contribution makes this inappropriate. Thus, in addition tothe manufacturing tolerances for the device, the fatigue and imprinthistory may vary within wide limits between different cells in the samememory device and even on the same bit line, and the parasitic currentmay depend strongly upon the device temperature at the time of readout.In addition, the parasitic current associated with a given non-addressedcell on the active bit line may depend on the actual logic state of thiscell. In that case the cumulative parasitic current from allnon-addressed cells on the active bit line depend on the set of datastored in those cells, which then must define prediction. Thus, thereare many drawbacks using a direct reference.

[0009] Reference levels can also be obtained from neighbouring cells todeal with the problems indicated above. The neighbouring cells arebelieved to have the same conditions as the read cells. However, this isnot always true, giving rise to problems.

[0010] Another implementation is to have a single current integratorproviding the signal level corresponding to a known polarization change.A non-unity gain amplifier then distributes this potential as thereference level to a number of sense amplifiers.

[0011] All of the above-described methods of obtaining a reference sharethe problem of non-predictable conditions, whereby there still is a needof another solution for obtaining a true reference.

[0012] Hence it is a primary object of the invention to improvereferencing of the sensing device, whereby the sensing device becomesresistant to noise and other interfering background signals. Anotherobject of the invention is to provide a sense amplifier, which is notinfluenced by cumulative signals from non-addressed cells during readingof stored data, obtained i.e. in a so-called “partial word read”.Finally, there is also an object of the invention to provide a readmethod for use with a sensing device of this kind.

[0013] The above-mentioned objects as well as other features andadvantages are realized according to the present invention with asensing device, which is characterized in that the sensing devicecomprises an integrator circuit for sensing the current response andmeans for storing and comparing two consecutive read values, one ofwhich is a reference value.

[0014] In an advantageous embodiment of the sensing device according tothe invention the integrator circuit comprises an operational amplifierand a capacitor connected between an inverting input of the operationalamplifier and the output thereof. Preferably the integrator circuit thencomprises a switch connected in parallel over the capacitor.

[0015] In an advantageous embodiment of the sensing device according tothe invention the means for two consecutive reads comprises a firstsample/hold circuit for sampling/storing a first read value, a secondsample/hold circuit for sampling/storing a second read value, and acomparator circuit connected to the outputs of the sample/hold circuitsfor determining the state of an addressed memory cell.

[0016] Preferably the sample/hold circuits then can comprise capacitorsand preferably can the comparator circuit be an operational amplifier.

[0017] Finally, a correction circuit can be connected between the secondsample/hold circuit and the output of the integrator circuit.

[0018] The above-mentioned objects as well as other features andadvantages are also realized according to the present invention with aread method which is characterized by two consecutive reads of a memorycell, integrating each read over a predetermined time periodrespectively to generate a first and a second read value, storing saidread values, comparing the stored read values, and determining a logicalvalue dependent on the sensed charge.

[0019] In an advantageous embodiment of the read method according to theinvention a time delay is introduced between two consecutive reads in aread cycle.

[0020] The invention will now be explained in more detail in conjunctionwith the appended drawing figures, wherein

[0021]FIG. 1 shows the principle of dual slope integration as used inthe invention,

[0022]FIG. 2 the principle shown in FIG. 1 in more detail,

[0023]FIG. 3a a generalized circuit diagram of a sensing deviceaccording to the invention,

[0024]FIG. 3b a variant circuit diagram of the sensing device in FIG.3a, and

[0025]FIG. 4 a circuit diagram of a sensing device with dual slopeintegration according to a preferred embodiment of the invention.

[0026] The invention implements a dual read which can be performedaccording to two principal schemes, termed (I) and (II) below.

[0027] (I) Dual read by means of a “single read” comprising a dualsensing operation, whereby word line WL is pulsed high once after a longbit line settling time followed by two successive reads (integrations).

[0028] (II) Dual read whereby a second read is subtracted from a firstread to determine a stored value. The advantage is that commonoffsets/mismatches are removed. The word line WL is pulsed twice andsensing is performed during each word line WL being high.

[0029] The dual read method has the purpose of reducing the effect ofthe background current and also provide a self-reference on a particularbit line. In FIG. 1 an integrated charge versus time graph is shown. Thedifference in magnitude of the background currents and the chargeemanating from the active cell is curve (i) as illustrated. Curve (ii)represents a logical “1” stored in the cell and curve (iii) a logical“0”. In this particular example a first read is performed between afirst time point t₁ and a second time point t₂ and a second read betweenthe second time point t₂ and a third time point t₃.

[0030] A more detailed relationship between the sensed charges can beseen in FIG. 2. Assuming an active cell containing a “1” during thefirst read between the first time point t1 and the second time point t2,first a read value ΔQ₁(“1”)=Q₄−Q₁is sensed, and during the second readbetween the second time point t2 and the third time point t3, a secondread value ΔQ₂(“1”)=Q₅−Q₄ is sensed in a similar manner. The first readvalue is stored in a first sample/hold circuit and the second read in asecond sample/hold circuit, as will be mentioned below. These can forinstance comprise a capacitor as charge storage element. Other chargestorage elements are of course also possible. This will be describedbelow in connection with a discussion of embodiments of the sensingdevice according to the invention.

[0031] In the same way for an active cell containing a “0” one getsΔQ₁(“0”)=Q₂−Q₁ and ΔQ₂(“0”)=Q₃−Q₂. But ΔQ₁ will in this example belarger than ΔQ₂ for both a “1” and “0”. Therefore, one has to introducea threshold level in order to distinguish a “0” from a “1”.

[0032]FIG. 3 shows schematically the principal functional components ofa sensing device 10 according to the invention, providing dual readcovering both the above-described principal sensing schemes (I) and(II). First a read, typically an integration of the current I_(BL) onthe bit line BL is performed by an integrator circuit 11 (inside thedashed line) comprising an integrating amplifier 12 with a non-invertinginput 13 and an inverting input 14, and a feedback capacitor C1connected in parallel between the non-inverting input 14 and the outputof the amplifier 12. First and second read values output from theintegrating circuit 11 are stored in first and second sample/holdcircuits 16;17 respectively. Each sample/hold circuit 16;17 has an inputfor a control signal CTRL1; CTRL2. A comparator, preferably anoperational amplifier 18 is connected with sample/hold circuit 16 viaits non-inverting input 19 and via its inverting input with sample/holdcircuit 17. The comparator compares two stored read values sensed in thedual read and generates the comparison as a data output signal on itsoutput D_(out).

[0033] If a hypothetical value, herein denoted V_(00-offset) isintroduced as the threshold level, one obtains the following conditionsfor the output.

[0034] ΔQ₁−ΔQ₂ >V_(00-Offset), which is interpreted as a “1”, and

[0035] ΔQ₁−ΔQ₂ >V_(00-Offset), which is interpreted as a “0”.

[0036] In this way, the error introduced by the background current, theoffset and process variation of the transistors in the integratingamplifier will manifest itself as a constant value in the ΔQ₁−ΔQ₂calculation. This error can be eliminated by adjusting the hypotheticalvalue V_(00-offset) in a correction circuit. FIG. 3b shows a variantembodiment of the device in FIG. 3a, but with the correction circuit 21connected between the second sample/hold circuit 17 and the output 15 ofthe integrator circuit 11.

[0037] Now FIG. 4 illustrating a preferred embodiment of the inventionshall be discussed. In this embodiment the sensing device 10 comprisesan integrator circuit 11 (inside the dashed line) with an operationalamplifier 12 having a non-inverting input 13, an inverting input 14, anoutput 15, and a feedback capacitor C1 connected between the output 15and inverting input 14 of the operational (integrating) amplifier 12. Inparallel to the feedback capacitor C1 there is provided a first switchSW1, which can be closed before sensing starts. The first switch SW1 isable to switch between at least two states, an open state and a closedstate, of which the open state is shown.

[0038] The feedback capacitor C1 is initially shorted allowing the bitline BL to be charged to the non-inverting input's 13 potential throughthe output stage of operational amplifier 12. The bit line potentialV_(BL) will differ from a switching level V_(S) by the input offsetV_(offset) of the operational amplifier 12. However, as long as themagnitude of the input offset voltage V_(offset) is small compared tothe total switching potential V_(s) of a memory cell, it can beneglected. When the first switch SW1 opens, a small amount of chargewill be injected onto the bit line BL from the capacitor C1 and must becancelled in a comparator 18, which is connected to the output 15 of theintegrator circuit 11. Subsequently current flowing to the bit line BLmust also flow through the feedback capacitor C1, resulting in apotential shift of Q/C, where Q is the charge from the active memorycell to be read and C is the feedback capacitance. Since the potentialon the bit line BL remains nearly constant, determined by the open loopgain of the operational amplifier 12, the total capacitance C_(BL) ofthe bit line BL does not affect the observed signal level. The magnitudeof the signal may also be established by judicious choice of the valueof the feedback capacitor C1.

[0039] The output 15 of the integrator circuit 11 is AC-coupled to thecomparator 18 via a capacitor C2, corresponding to the sample/holdcircuit 16. To provide an absolute reference a switch SW2 is connectedbetween ground and the output side of capacitor C2. In order to cancelout a transient from switch SW1, switch SW2 opens after the sensing bythe integrator circuit 11 starts.

[0040] It is possible to develop a self-referencing algorithm based onsequential integration of a single bit line BL. In this two-stagesensing, the integrator circuit 11 provides a self-reference to cancelout leakage currents and other common mode noise on the bit line BL. Asillustrated in FIG. 4, a third switch SW3 connected between the output15 via the second capacitor C2 which operates as the sample/hold circuit16 in FIG. 3a, and the non-inverting input of comparator 18, and afourth switch SW4 connected between ground and the inverting input ofcomparator 18 are provided for this purpose. The upper side of thefourth switch SW4 is via a third capacitor C3 which operates assample/hold circuit 17 in FIG. 3a connected to the output 15. Duringreset of the integrator circuit 11 comprising the operational amplifier12, the first switch SW1, the second switch SW2, and the third andfourth switches SW3 and SW4 are closed. The first switch SW1 opens tostart integration, followed by SW2 to latch the offset error introducedby opening the first switch SW1. After the first time period, the thirdswitch SW3 is opened, isolating the first time period integration value(cf. the period between time points t2 and t1 in FIG. 2) on the secondcapacitor C2. The fourth switch SW4 is opened (possibly before the thirdswitch SW3 opens) to begin integration during the second time period.Any leakage currents will appear as common mode signals to the inputs ofthe comparator 18 and thus cancel out, leaving only the chargedifferential arising from a polarization change. The periods ofintegration for the second and third capacitors C2 and C3 may beadjusted, as necessary, to establish appropriate margins for thecomparator 18.

[0041] The addressing scheme for performing a read according to theinvention using the inventive sensing device, shall now be described insome detail. During a read cycle the electric potentials on all word andbit lines are controlled in time according to a protocol or timingsequence whereby word line potentials are latched in a predeterminedsequence to potentials selected among predetermined word linepotentials, while bit lines are either latched in a predeterminedsequence to potentials selected among predetermined bit line potentialsor said bit lines are during a certain period of the timing sequenceconnected to circuitry that senses the charges flowing between the bitline(s) and the cells connecting to said bit line(s), two consecutivereads of said addressed cells are performed during the read cycle. Thetwo read values obtained are stored in the sample/hold circuits andfinally compared in the comparator of the sensing device.

[0042] Between said consecutive reads there may be a time or dwelldelay. The result of an integration of the current sensed by means ofthe sensing device performed during the first of the two reads in a readcycle to determine the logic value of an addressed cell (to determinewhether the cell contains a logic “0” or a logic “1”), is stored in thefirst sample/hold circuit. The read is always a destructive read endingup in a “0” and the memory cell must therefore be restored to itsinitial state (since a “1” or a “0” always ends up in a “0” because ofthe destructive read). The dwell delay is inserted to allow the materialin the memory cell to return to a relaxed condition. The second read isexecuted using an identical pulsing and sensing protocol as the one usedduring the first read. The result of the second read is evaluated in thesame way as the first read and stored in the second sample/hold circuit.The values stored in the first and second sample/hold circuits are thentransferred to the comparator for determining the state of the addressedcell. Since the consecutive reads expose the bit lines to the sameconditions in both cases, the offset currents are almost cancelled. Theuse of the same sensing device, typically the same integrating amplifiersimilarly, eliminates the concern over matching of circuit parametersand component values.

[0043] The dual slope integration particularly addresses a wide numberof potential problems in ferroelectric memories with a polymer memorymaterial. First, the comparison can be established with a margin closeto zero. Consequently, in a fatigued memory cell where the charge isreleased at a lower level and occurs slower, the sensing device willstill distinguish the state since the total charge released in a firsttime period is greater than that released in a subsequent (equivalent)time period. There is no need for a-priori knowledge of the level offatigue to properly sense the memory cell value. Similarly, followingimprint, the absolute magnitude of the charge released in any givenfirst time period is reduced due to the shift in the coercive field, butthe relative value is still ordered. Again, the state of the memory cellcan be determined with the dual slope integration without knowledge ofthe imprint magnitude. In an alternative embodiment of the invention itis possible to use a pre-read cycle immediately preceding the readoutcycle and differing from the latter in only one respect, namely that theactive word line is not shifted at all. The sensing device is thenactivated in precisely the same time slot relative to the bit linevoltage shifts as is the case in the subsequent read cycle. Thus, thecumulative charge detected during the pre-read cycle shall correspondvery closely to the parasitic current contributions captured during theread cycle, including contributions from the active cell. The detectedcharge from the pre-read cycle is stored and subtracted from thatrecorded during the read cycle, yielding the desired net charge from theswitching or non-switching transient in the active memory cell.

1. A sensing device (10) for reading data stored in a passive matrixmemory comprising memory cells in the form of ferroelectric capacitors,wherein said sensing device (10) senses a current response correspondingto the data, typically a binary one or a binary zero, and performs anintegration of two read values. characterized in that the sensing device(10) comprises an integrator circuit (11) for sensing the currentresponse and means (16,17,18) for storing and comparing two consecutiveread values, one of which is a reference value.
 2. A sensing device (10)according to claim 1, characterized in that the integrator circuit (1)comprises an operational amplifier (12) and a capacitor (C1) connectedbetween an inverting input (14) of the operational amplifier (12) andthe output (15) thereof.
 3. A sensing device (10) according to claim 2,characterized in that the integrator circuit comprises a switch (SW1)connected in parallel over the capacitor (C1).
 4. A sensing device (10)according to claim 1, characterized in that the means (16,17,18) for twoconsecutive reads comprises a first sample/hold circuit (16) forsampling/storing a first read value, a second sample/hold circuit (17)for sampling/storing a second read value, and a comparator circuit (18)connected to the outputs of the sample/hold circuits (16;17) fordetermining the state of an addressed memory cell.
 5. A sensing device(10) according to claim 4, characterized in that the sample/holdcircuits (16;17) comprise capacitors (C₂;C₃).
 6. A sensing device (10)according to claim 4, characterized in that the comparator circuit (18)is an operational amplifier.
 7. A sensing device (10) according to claim4 characterized in that a correction circuit (21) is connected betweenthe second sample/hold circuit (17) and the output (15) of theintegrator circuit (11).
 8. A read method for use with the sensingdevice according to claim 1, wherein the sensing device are used forreading data stored in a passive matrix memory with word and bit linesand comprising memory cells in the form of ferroelectric capacitors atcrossings between the word and bit lines, wherein the sensing devicesenses a current response corresponding to the data stored in a memorycell, typically at binary one or a binary zero, and performs anintegration of read values, wherein the read method comprisescontrolling the electric potentials on all word and bit lines in timelatching word line potentials to potentials selected among predeterminedword line potentials and either latching bit lines to potentialsselected among predetermined bit line potentials, wherein bit lines in aread cycle are connected to the sensing device for sensing a chargeflowing between a selected bit line and a memory cell at the crossing ofthe former and a word line activated by being latched to a selectedpotential for initializing the read cycle, characterized by performingtwo consecutive reads of a memory cell, integrating each read over apredetermined time period respectively to generate a first and a secondread value, storing said read values, comparing the stored read values,and determining a logical value dependent on the sensed charge.
 9. Aread method according to claim 8, characterized by introducing a timedelay between two consecutive reads in a read cycle.